TSuV structures are a key enabling technology for higher density electronic devices. Many packaging strategies currently under development seek to reduce the form factor of a packaged ICs. TSuV structures offer a means to meet increasing IC I/O requirements as footprint (area) of the chip continues to scale down. 3DIC initiatives further seek to stack multiple IC chips in piggy-back fashion to increase computing and/or storage density for a given package footprint. Such multi-chip integration schemes typically entail at least one TSuV to vertically interconnect the individual IC chips.
Presently however, fabrication cost and reliability of TSuV structures pose a problem for industry. Techniques and the associated structures for a conventional “via-last” TSuV process are illustrated in FIGS. 1A and 1B. As shown in FIG. 1A, an IC includes a substrate 100 upon which is formed circuit devices, such as transistors, capacitors, photodetectors, LEDs, lasers, and the like. The circuit devices are then interconnected through multiple levels of metal and interlayer dielectric, referred to herein collectively as the back end of line (BEOL) stack 120. A metallized pad 150 serves as an electrical interface between the IC and the external world. A via 135 is formed through the BEOL stack 120 and into a significant portion of the substrate 100. The via 135 is then lined with an electrical isolation layer 138 consisting of a suitably resistive dielectric. Upon the isolation layer 138 is a barrier layer 142, typically of a refractory material, such as titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The barrier layer serves, in one aspect, to inhibit the diffusion of the interconnection material (i.e., fill metal) that will subsequently be introduced in the via 135. Next, a suitable seed material 144 is deposited on the inner sidewall of the via 135 and on surfaces adjacent to the via 135. Suitable seed materials for the deposition of copper fill metal include copper (Cu), nickel (Ni), and cobalt (Co). A resist mask 130 is formed to leave only desired regions of the seed material 144 exposed.
Next, as shown in FIG. 1B, the fill metal 152, such as copper, is deposited, for example by electroplating, in a sufficient amount to fill the via 135. As shown, a significant amount of top side metal 151 is deposited over surfaces adjacent to the via 135 (i.e. non-via surfaces). Following fill of the via 135, the resist mask 130 is removed leaving the top side metal 151 to interconnect the pad 150 with the via 135. Typically, at least some portion of the top side metal 151 is considered overburden from the via fill process and necessitates removal, usually through chemical mechanical planarization (CMP). Finally, the substrate 100 is thinned to expose the bottom of the filled via 135, rendering a TSuV.
As illustrated, the conventional technique of forming a TSuV is generally based on the existing semiconductor processing techniques employed to form interconnects within the BEOL stack 120. While such reliance on existing techniques is understandable, inherent inefficiencies which may be tolerable in the context of BEOL processing are all the worse when applied to a TSuV. For example, with TSuVs being significantly larger and deeper than a BEOL via, problems with voiding and difficulties stemming from the amount of overburden 151 become all the more severe. CMP processing therefore becomes more complex and expensive with an attendant high consumables cost. A multiplicity of material layers, as well as poor step coverage of the isolation layer 138, the barrier 142, and/or the seed material 144 stemming from the aspect ratio (AR) and profile of the via 135 also limits scalability to >˜5 μm (micron) and AR<˜10. Finally, manufacturing yield is a more significant concern at the TSuV stage of processing, because each IC chip has a high value, having accumulated many hours of expensive processing time and thin film materials.
Therefore, TSuV structures with reduced defects (e.g., voids) and manufacturing techniques for such TSuV structures that reduce complexity are advantageous.